As feature sizes and device sizes shrink for integrated circuits, relative alignment between interconnect layers becomes of critical importance. Misalignment can severely impact the functionality of a device. Misalignment beyond certain minimum tolerances can render a device partly or wholly inoperative.
To insure that contacts between interconnect layers are made properly even if a slight misalignment occurs during masking steps, extra space is usually included in a design around contacts and other conductive features. This extra retained space is known as enclosure and results in the well known "dogbone" structure. Enclosure sizes of up to a few tenths of a micron are typical for 0.5 to 1.0 micron feature sizes.
Enclosure requirements are not consistent with the continued shrinkage of devices. Enclosure is not related to device functionality, but is due primarily to limitations in photolithography alignment capability and is used to insure that misalignment errors do not cause problems with the device. When designing devices having minimum feature and device sizes, minimizing enclosure requirements can significantly impact the overall device size.
Self-alignment techniques are generally known in the art, and it is known that their use helps minimize enclosure requirements. However, the use of self-alignment techniques has been somewhat limited by device designs in current use.
Conventional MOS FET devices are typically comprised of a gate electrode overlying a channel region and separated therefrom by a gate oxide. Conductive regions are formed in the substrate on either side of the gate electrode and the associated channel to form the source and drain regions. However, the majority of the area required for the source and drain regions is a function of the design layout and the photolithographic steps required, for example, to align the various contact masks and the alignment tolerances.
Conventionally, an MOS transistor is fabricated by first forming the gate electrode and then the source and drain regions, followed by depositing a layer of interlevel oxide over the substrate. Contact holes are then patterned and cut through the interlevel oxide to expose the underlying source and drain regions. A separate mask is required to pattern the contact holes. This separate mask step further requires an alignment step whereby the mask is aligned with the edge of the gate electrode which is also the edge of the channel region. There is, of course, a predefined alignment tolerance which determines how far from the edge of the gate electrode will be the minimum location of the edge of the contact. For example, if the alignment tolerance were 1 micron, the contact wall on one side of the contact would be disposed one micron form the edge of the gate electrode and the other side of the contact would be one micron from the edge of the nearest structure on the opposite side thereof, such as another conductive contact or interconnection line. In this example, the alignment tolerance would result in a source and drain having a dimension of two microns plus the width of the contact. The overall width is therefore defined by alignment tolerances, the width of the conductive interconnection and the minimal separation from adjacent structures. A significant amount of surface area is thus dedicated primarily to mask alignment causing a substantial loss of real estate when designing densely packed integrated circuits.
When MOS devices are utilized in a complementary configuration such as CMOS devices, the additional space required to account for alignment tolerances becomes even more of a problem. This space requirement is due to the fact that CMOS devices inherently require a greater amount of substrate and surface area than functionally equivalent P-channel FET devices.
This size disadvantage is directly related to the amount of substrate surface area required for alignment and processing latitudes in the CMOS fabrication procedure to insure that the N- and P-channel transistors are suitably situated with respect to P-well formation. Additionally, it is necessary to isolate N- and P-channel transistors from each other with fixed oxide layers with an underlying channel stop region. As is well known, these channel stops are necessary to prevent the formation of parasitic channels or junction leakage between neighboring transistors. Typically, the channel stops are highly doped regions formed in the substrates surrounding each transistor and effectively block the formation of parasitic channels by substantially increasing the substrate surface inversion threshold voltage. Also, they are by necessity the opposite in conductivity type from the source and drain regions they are disposed adjacent to in order to prevent shorting. This, however, results in the formation of a highly doped, and therefore, low reverse breakdown voltage, P-N junction. Of course, by using conventional technology with the channel stops, there is a minimum distance by which adjacent transistors must by separated in order to prevent this parasitic channel from being formed and to provide adequate isolation.
It would be desirable to have a planar integrated circuit having contact openings that meet design rule criteria while minimizing distances between the contacts and nearby active areas and devices.
It is therefore an object of the present invention to provide a method of forming improved contact openings between active areas and devices for scaled semiconductor devices.
It is a further object of the present invention to provide minimum contact enclosure for the contacts to the active areas.
It is a further object of the present invention to provide a method of forming the contact openings whereby the junction leakage is minimized and the device integrity is maintained.
It is yet a further object of the present invention to provide a method of increasing the planarity of the surface of the wafer thereby minimizing subsequent step coverage problems.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.